Staff SoC DFT Engineer, HBM
Core
Own SoC-level design for test (DFT) architecture and implementation for complex high-bandwidth memory (HBM) system-on-chip (SoC) base-die designs to enable manufacturability and silicon bring-up.
Role type
Staff SoC DFT Engineer (HBM)
Builds
HBM base-die SoC designs
Domain
Semiconductor / High-bandwidth memory (HBM) / Digital ASIC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC DFT architecture and implementation, scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), ATPG, RTL-to-GDS SoC flows, EDA tools (Siemens, Synopsys, Cadence), Python/Tcl/Perl scripting
Preferred skills
Large complex SoC integration with multiple IP blocks, RTL debugging and design analysis, memory system familiarity (DRAM, HBM, JEDEC specs)
Technologies
Siemens, Synopsys, Cadence, Python, Tcl, Perl
Responsibilities
Own SoC-level DFT architecture and implementation including scan, MBIST, LBIST, and boundary scan; Define and drive DFT architecture early in the design cycle; Implement and integrate DFT logic at block, subsystem, and full-chip levels; Execute and sign off DFT flows including linting, CDC checks, and coverage closure; Collaborate with physical design teams to optimize DFT solutions for placement, routing, and timing closure; Partner with verification, test, and manufacturing teams to ensure testability and smooth bring-up; Partner with CAD teams to standardize DFT flows and mentor engineers.
Seniority
Staff, hands-on IC with mentorship
