Staff HBM Design Architect - DFT
Core
Define and implement end-to-end DFT architectures for HBM base die and DRAM die to ensure quality, yield, and performance across complex multi-die architectures.
Role type
Staff HBM Design Architect (DFT)
Builds
Test architectures for next-generation HBM products
Domain
Semiconductor memory (HBM/DRAM) and 3D-stacked integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (test flows, access mechanisms)
Required skills
DFT architecture design, scan/MBIST/JTAG/boundary scan concepts, wafer probe and final test semiconductor flows, multi-die architecture testing
Preferred skills
HBM/DRAM/advanced memory product experience, TSV-based 3D integration knowledge, at-speed test techniques, DFT security features
Technologies
JTAG, MBIST, TSV, wafer probe, boundary scan
Responsibilities
Define end-to-end DFT architectures for HBM and DRAM die; Develop DFT strategies for stacked-die, cube-level, and system-level test flows; Architect test access mechanisms supporting wafer probe through final test; Enable silicon observability for yield learning, debug, and failure analysis; Collaborate across design, verification, layout, test, and manufacturing teams
Seniority
Staff, hands-on IC with strategic influence
