Principal Engineer - ASIC DV
Core
Lead ASIC Design Verification for IP/Block or Subsystem, ensuring first-pass product sign-off through comprehensive test plans and coverage analysis.
Role type
Principal ASIC Design Verification Engineer
Builds
Verified IP blocks and subsystems for memory and storage solutions
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, AMBA protocols (AXI/AHB), RTL debugging, Scoreboard design, Assertions, Functional coverage coding, Code Coverage analysis
Preferred skills
DDR protocol knowledge, Memory controller experience, Technically leading an IP/Block to completion
Technologies
System Verilog, UVM, AMBA, AXI, AHB
Responsibilities
Create verification test plans, develop System Verilog/UVM testbenches, lead and mentor verification engineers, ensure sign-off via coverage criteria, pair with global domain specialists
Seniority
Principal, hands-on IC with mentorship
