Staff Engineer, Design Verification Engineering
Core
Architect, implement, and manage metric-driven SystemVerilog and UVM verification environments for mixed-signal ICs, defining interfaces, state machines, and controlling logic for Data Center, Energy, and Automotive applications.
Role type
Staff Engineer, Design Verification Engineering
Builds
Production verification environments and test suites for analog and mixed-signal integrated circuits
Domain
Semiconductor / Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, mixed-signal simulation, Verilog-AMS, Real Number Models, logic synthesis, timing/power analysis, equivalence checking, ATPG, scripting (Perl/Python/C), verification tools (Xcelium/VCS)
Preferred skills
null
Technologies
SystemVerilog, UVM, Xcelium, VCS, Perl, Python, C, Verilog-AMS
Responsibilities
Define and verify interfaces, state machines, and controlling logic; Develop directed and constrained random test cases; Architect and manage complete metric-driven verification environments; Design and maintain mixed-signal simulation models; Implement custom digital interfaces (I2C, SPI, UART)
Seniority
Staff, hands-on IC