Senior Engineer IP Verification - AMS Verification
Core
Senior IC engineer responsible for verifying analog and mixed-signal circuits in DRAM memory products using simulation and formal methods.
Role type
Senior IC analog/mixed-signal verification engineer
Builds
Production-ready DRAM memory chips
Domain
Semiconductor / Memory / Analog & Mixed-Signal
Deliverable
production ML models | product features
Required skills
Analog/Mixed-Signal circuit design, SPICE testbench creation, Verilog A/MS/RVM modeling, SV/UVM verification, PSL assertions, complex circuit debugging, Virtuoso, Hspice, Xcellium, Simvision, Waveview
Preferred skills
Perl scripting, Python scripting, AI tool adoption for verification workflows
Technologies
Virtuoso, Primesim, Finseim, Hspice, Xcellium, Simvision, Waveview, Verilog, SystemVerilog, UVM, PSL, Perl, Python
Responsibilities
Build SPICE testbenches at block and full-chip levels, develop COSIM/mixed-signal verification environments, write Verilog models and UVM testbenches, debug complex analog/digital/mixed-signal circuits, leverage AI tools to improve verification methodology
Seniority
Senior, hands-on IC
