Senior/Staff Design for Test Engineer
Core
Architect, own, and implement comprehensive Design-for-Test (DFT) strategies for complex high-throughput digital pipelines in advanced CMOS nodes to ensure high test coverage and efficient test execution for next-generation AI accelerators.
Role type
Senior/Staff IC Design for Test Engineer (DFT)
Builds
Robust, testable silicon for rack-scale co-design of logic, data movement, packaging, optics, and interconnect in AI accelerators.
Domain
Semiconductor hardware design, AI accelerators, advanced CMOS nodes.
Deliverable
production ML models | product features
Required skills
DFT architecture and implementation, Scan insertion, ATPG, Boundary Scan, Memory BIST, SystemVerilog/Verilog/VHDL, Python/Tcl scripting, fault modeling, yield enhancement strategies
Preferred skills
Tape-out experience at 22nm or below, high-speed SerDes DFT, HBM/DDR DFT, AI/ML workload DFT, open-source DFT tool contributions
Technologies
SystemVerilog, Verilog, VHDL, Python, Tcl, IEEE 1149.1, IEEE 1687, EDA flows
Responsibilities
Architect and implement DFT strategy for high-throughput digital pipelines; Lead integration and verification of DFT features (Scan, JTAG, Boundary Scan, Memory BIST); Develop and optimize ATE-compatible test patterns; Drive RTL development with DFT architecture focus; Analyse and minimize DFT impact on PPA; Collaborate on mixed-signal and software DFT interfaces; Mentor junior engineers and lead DFT design reviews
Seniority
Senior/Staff, hands-on IC with mentorship
