ASIC Physical Design
1,420 open positions
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Digital Signal Processing and System Validation Engineer BroadcomUSA-California-San Jose-1320 Ridder Park Drive 1mo Designing digital signal processing blocks and validating ASIC architecture for next-generation optical data center connectivity products.
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Senior Physical Design Engineer MicrosoftUnited States, North Carolina, Raleigh 1mo End-to-end execution of physical design for large System-on-Chip (SOC) blocks, covering synthesis, place-and-route, and all signoff stages.
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Staff Physical Design Engineer-DPG-LPDDR MicronHyderabad - Phoenix Aquila, India 1mo Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes, driving floor planning, power planning, CTS, place & route, and physical signoff.
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Senior FPGA Circuit Design Engineer AlteraSan Jose, California, United States $149k–$149k1mo Design and develop complex FPGA circuits, programmable logic, and IP for next-generation FPGA products, optimizing for power, performance, area, timing, reliability, and yield.
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Senior Principal Engineer, Physical Design Engineering AnalogdevicesIndia, Bangalore, RMZ 1mo Lead SoC execution from spec to silicon, driving technical strategy and architecture for complex digital systems.
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Staff Engineer, Performance Modelling Renesas-ElectronicsNoida, UP, in 1mo Develop and maintain performance models for complex SoC designs using SystemC TLM 2.0 to optimize system efficiency and ensure successful product delivery.
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ASIC Engineer NVIDIAIndia, Bengaluru 1mo Develop and deploy innovative RTL design-quality methodologies (CDC, RDC, lint, structural checks) to improve RTL quality, project predictability, and silicon readiness.
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Digital IC Design Engineer (New Grad) MonolithicpowerHong Kong - China 1mo Design and implement digital and mixed-signal chips (SoC) for power management, automotive electronics, LED lighting, networking, and charging.
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Sr. Silicon Design Engineer↗ AMDAustin, TX, US 1mo Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, specifically focusing on ASIC development and complex integrated circuit layouts.
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IC Architect Engineer↗ Xg Tech Pte. Ltd.Clementi, S00, SG 1mo Define and drive the architecture of next-generation semiconductor products, balancing performance, power, area, and cost for intelligent vehicle SoCs.
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Technical Staff Engineer - Design↗ Microchip TechnologyBurnaby, BC, CA $107k–$107k1mo Designing next-generation storage and memory controller SoC products from concept to production, focusing on IO connectivity and pad ring definitions.
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Senior ASIC Design Engineer CiscoSan Jose, California, US $168k–$168k1mo Designing innovative hardware platforms (silicon, optics) for Cisco's core Switching, Routing, and Wireless products to power the AI era.
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Senior CPU Front End Methodology Engineer↗ Intel CorporationAustin, TX, US $164k–$164k1mo Design next-generation high-performance microprocessors by advancing front-end RTL methodologies, logic optimization, and AI-driven efficiency gains.
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Camera Power Engineer↗ QualcommSan Diego, CA, US $99k–$99k1mo Define, analyze, and optimize power consumption for multimedia cores (camera, video, computer vision) across the SoC design cycle to ensure efficiency in Snapdragon-powered devices.
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SoC Compute/Memory Subsystem Architect IntelIreland, Leixlip $75k–$75k1mo Define and drive end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms.
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Physical Design Engineer (Full-Chip / SoC-Level) - Singapore↗ ByteDanceSingapore, S00, SG 1mo Own the full chip / SoC from early physical planning through final GDS/tapeout, defining chip-level physical design strategy including die size, utilization, floorplanning, block partitioning, pin/bump planning, and clock architecture.
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
AmazonCupertino, California, United States
$157k–$157k1mo
Design and optimize high-performance, power-efficient custom SoCs (System on Chip) for AWS Machine Learning inference servers, specifically the Inferentia architecture.
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Sr Electrical Engineer - FPGA (Onsite)↗ Collins AerospaceCedar Rapids, IA, US $87k–$165k1mo Design, implementation, verification, and integration of high-performance ASICs, FPGAs, and SoPCs for avionics displays, computing, and networking products.
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Physical Design Engineer, AI Accelerator IP TenstorrentAustin $100k–$100k1mo End-to-end physical implementation of RISC-V CPU and AI accelerator IP blocks for external licensees, ensuring PPA targets and timing closure.
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Senior FPGA Architect – SystemVerilog↗ Keysight TechnologiesBarcelona, CT, ES 1mo Architect FPGA solutions for PathWave Test Sync Executive, a commercial software product delivering synchronization for Quantum, 6G, and Radar applications.
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Sr Digital Design Engineer↗ NXP SemiconductorsChandler, QC, CA 1mo Lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications.
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Template Job AsteralabsVancouver $133k–$133k1mo Design and implement complex digital blocks for rack-scale AI connectivity silicon, ensuring silicon-ready quality from microarchitecture to tapeout.
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Director, ASIC Design & Front-End Implementation HpeRoseville, California, United States of America 1mo Lead the ASIC Design and Front-End Implementation organization to deliver next-generation networking ASICs powering HPE Networking products.
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Silicon Architect OuraSan Francisco, CA, United States $180k–$180k1mo Define custom silicon architectures and roadmaps for next-generation wearable health products, translating system needs into silicon specifications.
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