ASIC Physical Design
2,687 open positions
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Expert Logic Design Engineer CiklumEspaña 17d Lead the architecture, design, and optimization of next-generation FPGA and ASIC-based control platforms for quantum computing systems.
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Physical Design Engineering Director AsteralabsToronto CA$200k–CA$250k18d Lead a team of physical design engineers to implement connectivity ASICs (retimers, signal conditioning) for high-speed serial interfaces in AI clusters and data centers.
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Staff DSP ASIC Design Engineer↗ NokiaKanata, Ontario, Canada 18d Develop and verify world-leading System-on-Chip (SoC) designs for optical networking, focusing on ASICs and FPGAs.
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Digital - Digital Design Engineer (title will reflect experience) Eliyan CorporationBay Area, Vancouver or Toronto 18d Developing micro-architecture specifications and RTL design descriptions for high-performance PHYs and Controllers in chiplet-based systems.
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Ingeniero/a FPGA↗ Tecnobit-Grupo OesíaRivas-Vaciamadrid, Community of Madrid, Spain 18d Design, develop, and integrate cryptographic algorithm solutions on FPGA for high-value client projects.
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Ingeniero/a FPGA↗ Cipherbit - Grupo OesíaRivas-Vaciamadrid, Community of Madrid, Spain 18d Design, develop, and integrate cryptographic algorithm solutions on FPGA for high-value client projects.
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Physical Design Technical Leader CiscoSan Jose, California, US $187k–$268k18d Lead end-to-end RTL-to-GDSII physical design implementation for next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs.
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Lead SoC Architect Advanced Micro Devices, IncSan Jose, California 18d Define overall SoC architecture and drive system-level innovation for next-generation chips deployed in AI, Data Center, Security, Communications, and Embedded Computing.
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Digital Design Engineering Intern Analog DevicesAssago, Provincia di Milano 18d Intern developing Low Iq solutions for Power Management Integrated Circuits (PMICs) for next generation Vital Signs monitoring ICs.
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Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies Renesas-ElectronicsSan Jose, CALIFORNIA, us 18d Lead workload and performance analysis, HW/SW optimization, and SoC architecture for AI workloads and complex IP/subsystems.
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Experienced Back-End Engineer CommITTel Mond 18d Physical Design Engineer responsible for taking customer SoC blocks from netlist to GDSII, including floorplanning, place & route, timing closure, and physical verification.
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(Sr./Staff) ISP RTL Design Engineer OmnivisionSingapore 19d Implementing ISP algorithms into hardware architecture for CMOS image sensors, optimizing for gate count and power.
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Principal Firmware Developer, HBM MicronFolsom, California, United States of America $181k–$308k19d Architect and implement firmware for next-generation Custom High Bandwidth Memory (HBM) products, enabling low-level programming and system control for large-scale AI datacenter environments.
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Architecture Technical Manager - NVLink Fusion NVIDIAUS, CA, Santa Clara $272k19d Drive cross-disciplinary architecture efforts for next-generation NVLink Fusion hardware and AI chips/chiplets.
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Principal Digital Design Engineer InfineonColorado Springs, CO 19d Design and architecture of state-of-the-art memory products and digital IPs, including SoC designs, RTL design, and DFT.
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STA - Lead Engineer QualcommChennai, Tamil Nādu, India 19d Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem.
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RTL Design Engineer↗ Ak Information Technologies Inc.Remote $135k–$146k19d Develop and verify register-transfer-level (RTL) designs for field-programmable gate arrays (FPGAs) and systems-on-chip (SoCs), turning system requirements into hardware designs.
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Static Timing Analysis Design Engineer / Physical Design NxpAustin (Oakhill, Office), US 19d Own end-to-end Static Timing Analysis (STA) and timing constraints for complex SoC designs from synthesis through final signoff to ensure timing closure on silicon.
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Principle FAE - IP/Silicon FAE ArmSeoul, South Korea 19d Provide technical leadership for Arm IP and Silicon products in Cloud AI, Physical AI, and Edge AI applications by partnering with semiconductor and AI accelerator companies to drive design wins and architecture decisions.
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Silicon Design Engineer↗ AMDTampines, S00, SG 19d Integrating RTL components from different design teams into AMD's next generation FPGA and programmable SOC products; building Full-Chip RTL connectivity models; verifying Full-Chip models match architectural intent; and developing custom tools and…
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SoC Design and Integration Engineer AppleAustin, United States of America 19d Design and integrate complex logic and IP blocks for high-performance, power-efficient system-on-chip (SoC) processors.
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IP Design PEY Intern AlteraToronto, Ontario, Canada CA$90k–CA$100k19d Develop and verify state-of-the-art FPGA IP cores for interfacing with external memories (DDR, LPDDR) and high-speed I/O devices (MIPI) for data center and machine learning applications.
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Senior VLSI Design Engineer CevaRa'anana, Israel 19d Lead full design flow of advanced DSP cores and baseband hardware accelerators for 5G modem IPs, serving User Equipment and satellite infrastructure.
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ASIC Senior Physical Design Engineer↗ Knowledge Development for Plastic Optical FiberMadrid, MD, ES 20d Deliver high-quality, timing-closed, DRC/LVS-clean layouts for complex digital SoCs in advanced optical networking ICs.
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?CPU Microarchitecture & Logic Design Engineer ↗ Guadalajara, JAL, MX 20d Design and implement high-performance execution units in CPU, optimizing for power, performance, and area (PPA) while refining microarchitecture and developing RTL.
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