Silicon Design Engineer
Core
Integrating RTL components from different design teams into AMD's next generation FPGA and programmable SOC products; building Full-Chip RTL connectivity models; verifying Full-Chip models match architectural intent.
Role type
Senior IC silicon design engineer (FPGA/SoC)
Builds
Next-gen FPGA and programmable SOC products
Domain
Semiconductor / Digital Logic Design
Required skills
RTL design, Verilog/SystemVerilog HDL, ASIC design flow, Full-Chip SoC RTL development, IP integration, Static Timing Analysis (STA), Linting, Unix/Linux scripting
Preferred skills
FPGA architecture, CAD tools (VCS, Verdi, Design Compiler, Primetime), Timing constraints, Revision Control (Perforce)
Technologies
Verilog, SystemVerilog, VCS, Verdi, Design Compiler, Primetime, Spyglass, Lint, Conformal, Perforce, Shell Scripts, Perl, Python
Responsibilities
Develop Full-Chip SoC RTL, Write Full-Chip Design Specification documents, Work with IP development teams to integrate IP components, Run lint and other static verification tools
Seniority
Senior, hands-on IC
