Principal Digital Design Engineer
Core
Design and architecture of state-of-the-art memory products and digital IPs, including SoC designs, RTL design, and DFT.
Role type
Principal Digital Design Engineer
Builds
Digital IPs, SoC designs, and memory products
Domain
Semiconductor / Digital Design / Memory Interfaces
Required skills
Digital circuit design, RTL design, DFT, STA, Low power design (UPF), HDL (Verilog/System Verilog), EDA tools (Synopsys/Cadence), Memory interface protocols (I2C, SPI, QSPI, xSPI)
Preferred skills
Non-volatile memory knowledge
Technologies
Synopsys, Cadence, Mentor Graphics, Verilog, System Verilog, UPF, DfT
Responsibilities
Design and architecture of state of the art memory products, Develop and execute technical strategies for digital IPs and SoC designs including architecture, RTL design, and DFT, Debug and resolve complex design issues including timing, power, and area optimization, Drive technical innovation and improvement, stay up to date with industry trends, and new design methodologies
Seniority
Principal, hands-on IC
