Physical Design Technical Leader
Core
Lead end-to-end RTL-to-GDSII physical design implementation for next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs.
Role type
Senior IC physical design technical leader (silicon photonics)
Builds
High-speed optical transceivers and driver ICs for AI/ML data centers
Domain
Semiconductor hardware / Silicon photonics / Optical networking
Required skills
Full-flow physical design (floorplan, place & route, signoff), EDA tool flows, Python/TCL/Shell automation, Mixed-signal macro placement, STA timing closure, Power grid design, Electromigration/IR drop analysis, Functional equivalence checking
Preferred skills
High-speed/high-density macro-dominant blocks, SDC timing constraint creation, Mixed-signal integration, Standard-Cell IP selection
Technologies
Python, TCL, Shell, EDA tools (Synopsys/Cadence implied), GDSII, RTL
Responsibilities
Lead hierarchical floorplanning and complex mixed-signal macro placement, Architect and scale digital implementation flows with automation, Collaborate with RTL, Analog, DFT, Packaging, and CAD teams to resolve cross-domain bottlenecks, Drive signoff (STA, IR/EM, PV) to ensure first-pass silicon success
Seniority
Senior, hands-on IC
