Staff/ Senior Staff Engineer, STA
Core
Drive timing closure and signoff readiness for block-level and full-chip VLSI designs across all operating modes and process corners.
Role type
Senior IC VLSI STA Engineer
Builds
High-performance, power-efficient SoCs for Automotive, Industrial, Infrastructure, and IoT
Domain
Semiconductor / VLSI Design
Required skills
Static Timing Analysis (STA), timing closure, setup/hold analysis, OCV/AOCV/POCV modeling, clock tree concepts, SDC constraints, ECO implementation, Synopsys PrimeTime/Cadence Tempus, Tcl/Perl/Python scripting
Preferred skills
Low-power timing analysis (UPF/CPF), signal integrity (SI) awareness, variation-aware signoff, flow automation
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Perl, Python
Responsibilities
Perform block-level and full-chip STA across all modes and corners; Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity violations; Develop and validate timing constraints (SDC); Partner with RTL, Synthesis, CTS, and Physical Design teams; Drive timing closure through ECO and optimization; Perform pre-layout and post-layout timing analysis; Review timing exceptions (false paths, multicycle paths); Generate timing reports and closure metrics; Establish STA methodologies and automation.
Seniority
Senior, hands-on IC
