Sr Physical Design Engineer
Core
Physical Design Engineer responsible for RTL-to-GDS implementation of high-performance, multi-gigabit SerDes PHY and advanced IP designs.
Role type
Senior IC Physical Design Engineer
Builds
High-performance SerDes PHY and advanced IP blocks
Domain
Semiconductor / Digital IC Design
Required skills
RTL-to-GDS physical design flow, timing-driven place and route, clock tree synthesis, physical verification, logic equivalence checking, EDA tools, design optimization
Preferred skills
High-speed SerDes PHY experience, automated design flows, Verilog, floorplanning, IP integration, timing/power/area optimization, design methodology development
Technologies
Synopsys/Cadence EDA tools, Verilog, Schematic/Layout/Simulation tools
Responsibilities
Drive physical implementation of RTL blocks, develop automated design flows, analyze and optimize designs for timing/power/area, support floorplanning and IP integration, perform quality checks, troubleshoot implementation issues, improve automation and design cycle time
Seniority
Senior, hands-on IC
