Director, Cache RTL
Core
Lead the Cache Hierarchy RTL organization responsible for L2 and L3 cache designs in AMD's next-generation CPU cores, owning microarchitecture, RTL implementation, and design quality from feature definition through tapeout.
Role type
Senior IC Director (Cache RTL & Microarchitecture)
Builds
High-performance, energy-efficient L2/L3 cache designs for AMD server, client, and gaming products
Domain
Semiconductor / CPU Design / Cache Hierarchy
Required skills
Cache architecture development, RTL implementation (Verilog/SystemVerilog), Microarchitecture design, People leadership (managing managers), Cross-functional partnership, Design quality flows (lint, CDC/RDC, formal), Scripting, Hardware design experience
Preferred skills
CPU Coherency and Coherent NOC experience, Cache Allocation and Replacement Policy, Low-power design techniques, RAS features (ECC), IP reuse and configurability, AI-assisted engineering methodology
Technologies
Verilog, SystemVerilog, Lint, CDC/RDC, Formal verification, ECC
Responsibilities
Lead functional L2 and L3 cache RTL teams with full ownership of microarchitecture and RTL implementation; Partner with architects to translate architecture into optimized microarchitecture; Own RTL execution across multiple concurrent programs and product generations; Partner with Physical Design, Verification, and DFT teams to ensure quality and manufacturability; Recruit, develop, and retain top engineering talent; Represent the organization in cross-functional and executive reviews
Seniority
Director, hands-on IC with people leadership
