(Sr./Staff) ISP RTL Design Engineer
Core
Implementing ISP algorithms into hardware architecture for CMOS image sensors, optimizing for gate count and power.
Role type
Senior IC RTL design engineer (ISP)
Builds
ISP hardware architecture and logic for image sensors
Domain
Semiconductor / Image Signal Processing
Required skills
Verilog, SystemVerilog, SystemC, High Level Synthesis, CMOS Image Sensor knowledge, Digital Design, Logic Verification, Power Optimization, Gate Count Optimization
Preferred skills
Catapult HLS tool, C++, System C
Technologies
Verilog, SystemVerilog, SystemC, Catapult HLS
Responsibilities
Implement ISP algorithms into hardware using Verilog/SystemVerilog/SystemC; Define ISP hardware architecture based on product features and performance requirements; Verify logic at ISP and digital system levels; Optimize design for low gate count and power consumption; Collaborate with ISP algorithm team.
Seniority
Senior, hands-on IC
