ASIC Physical Design
1,420 open positions
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Senior Director, Hardware SonicWallRemote 1mo Lead R&D and multi-disciplinary development of hardware systems including servers, firewalls, security appliances, switches, and access points.
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Staff Design Engineer, HBM Architecture MicronRichardson, TX, US $146k–$146k1mo Architect, design, and optimize high-speed datapath circuitry for next-generation High Bandwidth Memory (HBM) products, focusing on logic-die and core-die architectures to enable industry-leading bandwidth, power efficiency, and reliability.
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Transceivers & Protocol IP Application Engineer AlteraSan Jose, California, United States $149k–$149k1mo Trusted technical advisor guiding customers and partners through the full FPGA design cycle for high-speed transceiver and protocol IP solutions, from architecture selection to production readiness.
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Lead Design Engineer CadenceHYDERABAD 1mo Lead the end-to-end RTL design, micro-architecture definition, and integration of complex SoC, subsystem, and IP blocks.
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ASIC Design Engineer 2 HpeSunnyvale, California, United States of America $106k–$214k1mo Design high-speed ASICs for cutting-edge networking chips used in world-class routers and switches, handling tasks from micro-architecture specification to timing closure and debugging.
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Sr Staff Engineer, STA Renesas-ElectronicsBengaluru, KA, in 1mo Own RTL-to-Gate conversion, constraint development, and timing closure to deliver high-performance, low-power chips.
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ASIC Physical Design Engineer (RDSS Intern) NVIDIATaiwan, Hsinchu 1mo Physical design of digital chips from RTL frozen to tape out, focusing on synthesis, formal verification, timing closure, and flow automation.
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Chip Design Engineer, Nitro Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
1mo
Design and implement complex hardware blocks and microarchitecture for AWS Nitro, the network and cloud management controller powering millions of servers.
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R&D Engineer IC Design BroadcomUSA-CA Irvine Alton Parkway Bldg 2 $151k–$151k1mo Conceive and develop leadership silicon technology for AI/ML and cloud operators, specifically focusing on Ethernet/IP switching for multi-scale data centers.
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Hardware Engineer CiscoHsinchu, Taiwan 1mo Lead hardware design for next-generation Hyperscaler Switches using Silicon One and/or merchant ASICs, focusing on system and board-level specifications, FPGA design, and bring-up.
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Principal Digital Design Engineer AnalogdevicesItaly, Bari $69k–$69k1mo Lead the development of the digital part of new mixed-signal products (ASSP and FPGA) for healthcare applications, driving projects from architecture through tape-out.
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Digital IC Designer ON SemiconductorWaterloo, ON, Canada $102k–$102k1mo Designing digital subsystems and embedded MCU/DSP for low-power mixed-signal SoCs that sense and connect the world or manage personal health.
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CPU Floorplan Lead IntelIndia, Bangalore 1mo Defines physical dimensions of CPU IP, optimizes die size and technology selection, and integrates dies in a package for tapeout.
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Senior RTL Design Engineer SambanovasystemsAustin, TX $120k–$120k1mo Design component units of the Reconfigurable Dataflow Unit (RDU) ASICs for SambaNova's full-stack generative AI platform, covering RTL implementation, PPA trade-offs, and silicon bring-up.
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Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
AmazonCupertino, California, United States
1mo
Design and optimize hardware for cloud server platforms, specifically focusing on Static Timing Analysis (STA) for AWS Inferentia and other ML inference products.
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Digital IC Design Engineer Texas InstrumentsSanta Clara, CA, United States 1mo Architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for Audio-Video solutions in automotive ADAS and IVI systems.
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SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
AmazonCupertino, California, United States
$136k–$136k1mo
Model and estimate power consumption for machine learning accelerator SoCs (Inferentia and Trainium) from RTL to netlist stages to optimize datacenter AI workloads.
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Research Fellow (Digital IC design and EDA) NtuNTU Main Campus, Singapore 1mo Conduct independent research on open-source processor and accelerator architectures, specifically RISC-V based designs and AI accelerators, while developing innovative hardware design methodologies.
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Digital SoC ASIC Physical Implementation Engineer (f/m/div.) Bosch-GroupDresden, SN, de 1mo Implement mixed-signal SoC ASICs with microcontroller architectures through to the digital layout for next-generation automotive radar applications.
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Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
AmazonAustin, Texas, United States
$159k–$215k1mo
Design and optimize hardware methodologies for custom ML accelerator chips (AWS Inferentia, Trainium) in advanced nodes to enable cloud-scale machine learning.
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Staff Engineer AI/ML GlobalFoundriesSanta Clara, US $143k–$143k1mo Lead RTL development and micro-architecture design for AI-enabled RISC-V CPU cores, including vector extensions and matrix engines.
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?FPGA-Entwickler VHDL (m/w/d) Bremen, BREMEN 1mo Designing and implementing digital circuits on FPGA platforms, verifying designs, and integrating modules into hardware/software systems.
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