Senior VLSI Design Engineer
Core
Lead full design flow of advanced DSP cores and baseband hardware accelerators for 5G modem IPs, serving User Equipment and satellite infrastructure.
Role type
Senior IC VLSI design engineer (5G baseband)
Builds
Licensable 5G modem IP cores and hardware accelerators for transmit/receive chains
Domain
5G cellular communication, satellite infrastructure, digital signal processing
Required skills
RTL design (Verilog/SystemVerilog), synthesis, timing analysis, SoC architecture, low-power techniques, EDA tools (Synopsys, Cadence, Siemens EDA/Mentor), digital design principles
Preferred skills
Signal processing, digital communication systems, CDC/RDC analysis, DFT, multi-power-domain design, licensable IP delivery
Technologies
Verilog, SystemVerilog, Synopsys, Cadence, Siemens EDA, Mentor
Responsibilities
Design and implement high-performance 5G baseband DSP cores and hardware accelerators; Develop programmable DSP architectures for multi-antenna and satellite systems; Own design flow from architecture/RTL through verification support, synthesis, and timing closure; Optimize PPA with backend and cross-functional teams; Collaborate with algorithm, verification, backend, software teams, and customers from specification to silicon bring-up
Seniority
Senior, hands-on IC
