Digital Design Engineering Intern
Core
Intern developing Low Iq solutions for Power Management Integrated Circuits (PMICs) for next generation Vital Signs monitoring ICs.
Role type
Digital Design Engineering Intern
Builds
Low Iq PMICs for Vital Signs monitoring
Domain
Semiconductor / Analog & Digital IC Design
Required skills
RTL development (Verilog/System Verilog), Design Verification (UVM), Low Power Design, Logical Synthesis, Static Timing Analysis, Power Analysis, Physical Implementation, Design For Testability, Asynchronous Digital Design, FPGA experience, Microcontroller architecture knowledge, VLSI basics
Preferred skills
RISC-V Firmware Development and Validation, IC bench evaluation (Oscilloscopes, Multimeter, Power Source, Function Generator)
Responsibilities
Interact with cross-functional teams, Develop Low Iq PMIC solutions, Internally train on RTL development, Linting, Clock/Reset Resynchronization, Design Verification, Low Power Design, Logical Synthesis, Static Timing Analysis, Power Analysis, Physical Implementation, Design For Testability, Asynchronous Digital Design, Lab Measurements
