Experienced Back-End Engineer
Core
Convert customer SoC blocks from netlist to GDSII, handling floorplan, place & route, clock tree synthesis, timing closure, power grid analysis, and physical verification sign-off.
Role type
Senior IC physical design engineer (back-end)
Builds
GDSII layouts for advanced SoCs (180nm to 2nm nodes)
Domain
Semiconductor manufacturing / ASIC physical design
Required skills
Floorplanning, Place & Route, Static Timing Analysis (STA), Clock Tree Synthesis (CTS), Power grid analysis, LVS/DRC debug
Preferred skills
DFT, Synopsys IC Compiler (ICC/ICC2)
Technologies
Synopsys IC Compiler, TSMC process nodes
Responsibilities
Perform floorplanning and place & route for customer SoC blocks
Seniority
Senior, hands-on IC