IP Design PEY Intern
Core
Develop and verify state-of-the-art FPGA IP cores for interfacing with external memories (DDR, LPDDR) and high-speed I/O devices (MIPI) for data center and machine learning applications.
Role type
FPGA IP Design Intern
Builds
Configurable intellectual property (IP) cores integrated with Quartus Prime CAD tools
Domain
Semiconductor / FPGA / High-speed I/O interfaces
Required skills
RTL development (SystemVerilog, Verilog, VHDL), Digital logic hardware design, Verification methodologies, Scripting (Python, TCL, Perl, C/C++)
Preferred skills
FPGA design experience, RTL simulation, Timing closure, Static timing analysis, DDR/LPDDR/MIPI hardware interface experience
Technologies
Quartus Prime, SystemVerilog, Verilog, VHDL, Python, TCL, Perl, C/C++, DDR, LPDDR, MIPI
Responsibilities
Architecture and design based on protocol specifications for DDR, LPDDR, and MIPI devices; RTL development; Verification (verification IP, frameworks, regression tests); Hardware power-on and debug; New product release support; Customer technical support
Seniority
Intern
