Experienced Back-End Engineer
Core
Physical Design Engineer responsible for taking customer SoC blocks from netlist to GDSII, including floorplanning, place & route, timing closure, and physical verification.
Role type
Senior IC physical design engineer
Builds
GDSII layouts for advanced SoCs
Domain
Semiconductor / ASIC design
Required skills
Floorplanning, Place & Route, Static Timing Analysis (STA), Clock Tree Synthesis (CTS), Power grid analysis, LVS/DRC debug
Preferred skills
DFT, Synopsys IC Compiler (ICC/ICC2)
Technologies
Synopsys IC Compiler, TSMC process nodes
Responsibilities
Floorplan, place & route, clock tree synthesis, timing closure, power grid analysis, physical verification sign-off
Seniority
Senior, hands-on IC