Senior Digital Engineer
Core
Designing power and area-optimized digital circuits for complex mixed-signal applications including data conversion and power management.
Role type
Senior Digital Design Engineer (ASIC/SoC)
Builds
Mixed-signal data conversion and power management silicon products
Domain
Semiconductor / Mixed-signal / Power Management
Required skills
Digital RTL design (Verilog/SystemVerilog), ASIC design methodology, Timing analysis and closure, Low-power design techniques, DFT strategy, Block-level verification, Debugging RTL and gate-level simulations
Preferred skills
Mixed-signal design methodologies, Design constraints and P&R hand-off, Static Timing Analysis (STA), Power analysis and optimization, UVM verification, AMBA or I2C protocols
Technologies
Verilog, SystemVerilog, UPF, Lint, CDC, RDC, STA, UVM, AMBA, I2C
Responsibilities
Architect and design low-power digital circuits for mixed-signal data conversion and power management; Integrate design at the top level and run block & top-level simulations; Collaborate with Analog and Verification engineers to deliver high-quality silicon solutions; Develop detailed block & chip level design documents; Perform silicon evaluation and document device errata; Participate in design reviews and ensure adherence to project goals
Seniority
Senior, hands-on IC
