Staff Silicon Design Engineer – Physical Design
Core
Staff Silicon Design Engineer responsible for RTL/netlist-to-GDS implementation, timing closure, and physical verification for next-gen processors.
Role type
Staff Silicon Design Engineer (Physical Design)
Builds
Next-generation processors and AI chips
Domain
Semiconductor / Silicon Design
Deliverable
production ML models
Required skills
Floorplanning, Placement, CTS, Routing, Timing Closure (STA), Physical Verification (DRC/LVS), Power Planning, ECO development, Tcl/Python/Perl/Shell scripting, AI-assisted workflow validation
Preferred skills
Hierarchical design integration, Low-power design (EM/IR), Advanced node experience, Reusable flow development
Technologies
Synopsys Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC, Calibre, Tcl, Python, Perl, Shell
Responsibilities
Own or contribute to RTL/netlist-to-GDS implementation; Drive timing closure through STA and SDC debugging; Support hierarchical physical design and integration; Resolve challenges in timing, congestion, clocking, power, area, and signal integrity; Support signoff checks; Build reusable automation; Use and validate AI coding assistants; Collaborate with RTL, circuit, and global engineering teams.
