ASIC Digital Design Tech Lead
Core
Architect the backbone of next-generation optical interconnects and own the full ASIC lifecycle from concept to tapeout for Cisco's core Switching, Routing, and Wireless products.
Role type
Senior IC ASIC Digital Design Technical Lead
Builds
High-speed optical interconnects, 100G/200G/400G silicon photonics, and Co-Packaged Optics
Domain
Semiconductor / Optical Interconnects / High-Performance Computing
Required skills
RTL design, CPU subsystems, SoC design, FSMs, FPGA validation, ASIC design flow management, SerDes, D2D PHY IP, high-speed datapath, low-speed control plane, synthesis, timing closure, DFT, low-power design, design automation scripting
Preferred skills
End-to-end silicon lifecycle architecture, microarchitecture design, verification coverage analysis, IP integration, backend implementation, cross-functional leadership
Technologies
SerDes, D2D IP, ODSP, AXI, SPI, I2C, APB, Ethernet, PAM4, FPGA, GDS2
Responsibilities
Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up; Translate top-level requirements into high-speed datapath and low-speed control plane block specifications; Independently simulate and debug complex design issues and support IP integration; Support synthesis, DFT, low-power design, and timing closure while developing automation scripts; Partner with cross-functional teams to resolve technical design challenges.
Seniority
Senior, hands-on IC with leadership responsibilities
