Physical Design Senior Staff Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products, with a focus on PNR implementation for Qualcomm SoCs.
Role type
Senior Staff IC physical design engineer (SoC)
Builds
ASIC blocks and System-on-Chip (SoC) designs for next-generation communication and data processing products
Domain
Semiconductor / ASIC Physical Design
Required skills
Floorplanning, Placement, Clock Tree Synthesis (CTS), Post-route optimization, Static Timing Analysis (STA), Power analysis, Formal Verification (FV), Low power verification, Physical Verification (PV), LEC/CLP/PDN knowledge, Unix/Linux scripting (Perl/TCL)
Preferred skills
Experience with latest tech nodes (4nm/5nm/7nm/10nm)
Technologies
4nm, 5nm, 7nm, 10nm, Perl, TCL
Responsibilities
Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route, etc) on latest nodes; Perform signoff activities (STA, Power analysis, FV, low power verification, PV, etc)
Seniority
Senior Staff, hands-on IC
