Physical Design Engineering Director
Core
Lead a team of physical design engineers to implement connectivity ASICs (retimers, signal conditioning) for high-speed serial interfaces in AI clusters and data centers.
Role type
Senior IC Physical Design Engineering Director
Builds
High-speed connectivity ASICs (PCIe, Ethernet, NVLink, CXL) for hyperscale AI infrastructure
Domain
Semiconductor / High-speed SerDes / AI Infrastructure
Required skills
Physical design flow (synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS), Cadence Innovus, Synopsys Fusion Compiler/ICC2, Tcl/Python/Perl scripting, team leadership, floorplanning, SerDes integration
Preferred skills
High-speed SerDes physical layer (equalization, CDR, signal integrity), EDA automation (agentic AI), scaling physical design teams
Technologies
Cadence Innovus, Synopsys Fusion Compiler, ICC2, Tcl, Python, Perl, TSMC advanced nodes
Responsibilities
Build and mentor a physical design team for Signal Connectivity Group products; Drive block and top-level physical design from floorplan to tapeout; Collaborate with RTL, DFT, STA, and verification teams; Work with IP vendors for RTL and hard-macro integration; Establish physical design best practices and flow improvements; Coordinate with global PD teams for consistent methodology
Seniority
Director, hands-on IC leadership
