Static Timing Analysis Design Engineer / Physical Design
Core
Own end-to-end Static Timing Analysis (STA) and timing constraints for complex SoC designs from synthesis through final signoff to ensure timing closure on silicon.
Role type
Senior IC physical design engineer (static timing analysis)
Builds
Timing-closed SoC designs for advanced semiconductor products
Domain
Semiconductor / ASIC / SoC Physical Design
Required skills
Static Timing Analysis (STA) methodologies, Timing Constraints development and validation, Timing ECO generation (automated and manual), Timing correlation and path debugging, Python scripting, TCL scripting, Perl scripting, Advanced node implementation (≤ 16nm/5nm), Synopsys flows
Preferred skills
High-reliability SoC experience, AI-driven design methodologies and automation
Technologies
Synopsys flows, Python, TCL, Perl
Responsibilities
Drive timing constraints creation and validation, Work with Frontend, IP, and DFT teams to resolve timing issues, Perform timing correlation and debug failing paths from synthesis to signoff, Provide timing feedback during all design stages, Create automated and manual timing fixes, Support post-silicon bring-up and yield improvement.
Seniority
Senior, hands-on IC
