Senior Staff Engineer, Physical Design
Core
Lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes, ensuring alignment with overarching SoC strategies.
Role type
Senior Staff IC physical design engineer (subsystem/block level)
Builds
Subsystem and block-level physical implementations for SoCs
Domain
Semiconductor / SoC physical design
Required skills
Timing closure, congestion analysis and resolution, power integrity, clocking methodologies, floorplanning, RTL design collaboration, verification collaboration, backend team collaboration, low-power design techniques, scripting automation (Tcl, Python, Perl)
Preferred skills
SoC-level floorplanning, clock domain partitioning, clock tree architecture, skew management, clock gating
Technologies
Synopsys ICC2, Fusion Compiler, PrimeTime, Cadence Innovus, Tempus, Certus
Responsibilities
Lead block- and subsystem-level physical design closure, collaborate with SoC-level teams on clocking and floorplanning, develop and scale closure methodologies, mentor physical design engineers, work cross-functionally with RTL/STA/power/verification teams, mitigate physical design risks
Seniority
Senior Staff, hands-on IC with mentorship
