STA - Lead Engineer
Core
Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem.
Role type
Lead Static Timing Analysis (STA) Engineer
Builds
SoC and SubSystem designs meeting timing and power constraints
Domain
Semiconductor Hardware Engineering (SoC Design)
Required skills
Static Timing Analysis (STA), Timing Analysis & Debug, Flow Optimization, Methodology Development, Low-Power Techniques, ECO Timing Flow
Preferred skills
Clock gating, Power gating, Multi-voltage designs, Logical equivalence checks
Technologies
PrimeTime, Tempus, TCL, Perl, Python
Responsibilities
Validate and debug timing across multiple PVT conditions; Run STA flows and correlate Spice to STA results; Evaluate timing methodologies/tools across technology nodes and automate STA/PD flows; Handle timing ECOs (DMSA, tweaker, PrimeClosure) and logical equivalence checks; Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.
