Formal Validation Engineer
Core
Develop comprehensive formal verification for complex micro-architectures and IP blocks (CPU, Cellular, Audio, Neural Networks, Security, etc.) to prove properties, find bugs, and improve chip design.
Role type
Senior IC formal verification engineer (hardware/SoC)
Builds
Verified micro-architecture specifications and correct-by-construction design methodologies for Apple Silicon SoCs
Domain
Semiconductor hardware design and verification
Required skills
formal verification, Verilog, System Verilog, C, C++, digital logic design, computer architecture, RTL debugging, regression testing, coverage analysis, scripting
Technologies
Verilog, System Verilog, C, C++, formal verification tools
Responsibilities
Develop formal micro-architecture specifications, create comprehensive verification test plans, architect correct-by-construction design methodologies, develop reusable formal models and verification code, debug RTL and analyze failing designs, drive cross-functional engineering deliverables
Seniority
Senior, hands-on IC
