FE Engineer
Core
Design and performance modeling for vertical product models, correlating RTL performance against model performance to debug bottlenecks and improve design efficiency.
Role type
Senior IC computer architecture engineer (performance modeling & verification)
Builds
Performance models, testbench infrastructure, and data analysis methodologies for chip design
Domain
Semiconductor / Computer Architecture
Deliverable
production ML models
Required skills
Computer Architecture (Cache Coherency, Cache Hierarchy, Fabric Interconnect), Data Structures and Algorithms, SystemVerilog, C++, Python, Perl, Waveform viewers, Design Verification
Preferred skills
N/A
Technologies
SystemVerilog, C++, Python, Perl
Responsibilities
Correlate RTL performance against model performance; Identify performance bottlenecks and coordinate with Architecture to improve performance; Develop testbench infrastructure for monitoring on-chip activity; Architect and implement data analysis and visualization methodologies for simulation performance data; Review results and analysis of performance validation work with cross-functional audiences.
Seniority
Mid-level, hands-on IC
