Senior Digital Design Verification Engineer
Core
Senior Digital Design Verification Engineer owning verification of complex digital blocks and major SoC features for power management chips.
Role type
Senior IC digital design verification engineer
Builds
Power management SoCs for AI, datacenter, enterprise computing, networking, and high-performance power delivery
Domain
Semiconductor / Power Management / Digital Design
Required skills
SystemVerilog, UVM, constrained random verification, functional coverage, SystemVerilog Assertions, RTL debug, testbench development, regression automation, scripting (Python/Bash/Perl/Tcl), digital design fundamentals (FSMs, clock domains)
Preferred skills
SoC verification, mixed-signal verification, embedded processor interfaces, control protocols (PMBus, I2C, SPI), simulation tools (Xcelium, VCS, Verdi), formal verification, silicon bring-up
Technologies
SystemVerilog, UVM, Python, Bash, Perl, Tcl, Cadence Xcelium, SimVision, Synopsys VCS, Verdi, JasperGold
Responsibilities
Own verification of complex digital blocks from planning to closure; Develop feature-based verification plans; Build reusable UVM environments; Develop constrained random and targeted tests; Drive coverage closure; Debug RTL and testbench failures; Automate regression workflows; Provide technical guidance to junior engineers
Seniority
Senior, hands-on IC
