Principal/Team Lead, Digital Verification Engineer (FEC)
Core
Develop verification strategies, test plans, and testbenches to simulate and validate functional blocks and subsystems for Ciena's Forward Error Correction (FEC) IP.
Role type
Principal/Team Lead Digital Verification Engineer (ASIC)
Builds
Verified functional blocks and subsystems for high-speed connectivity modems
Domain
Telecommunications / Digital ASIC Verification
Required skills
System Verilog, UVM, C++, formal verification, coverage-driven verification, regression monitoring, debugging, team leadership, mentoring
Preferred skills
Forward Error Correction (FEC) domain knowledge, DSP background, Python, bash, Jira, GIT
Technologies
System Verilog, UVM, C++, Python, Jira, GIT
Responsibilities
Develop verification and functional coverage test plans; Create testbench environments, agents, and test scenarios; Validate architectural FEC functional blocks using simulation and formal methods; Mentor and supervise junior verification engineers; Communicate verification progress and risks to stakeholders
Seniority
Principal, hands-on IC with team leadership
