FE Engineer
Core
Analyze RTL and design performance in complex SoCs, identify bottlenecks, and correlate RTL performance against model performance.
Role type
Senior IC verification/performance engineer (SoC)
Builds
Performance analysis reports, debug methodologies, and optimized SoC designs
Domain
Semiconductor / Computer Architecture
Required skills
Computer Architecture (Cache, CPU operations), Verilog/System Verilog, UVM testbench development, Python/Perl scripting, SoC Fabric/Interconnect design, Waveform debugging (Verdi/Indago), Data visualization (Excel/CSV)
Responsibilities
Correlate RTL performance against model performance, identify performance bottlenecks in design, define performance statistics for debugging, lead collaborations between Design, DV, and Architecture stakeholders, design experiments to isolate issues, debug waveforms to analyze cycle-by-cycle operations
