Lead DFT Engineer (Scan Insertion | ATPG | MBIST )
Core
Lead DFT Engineer responsible for implementing and verifying DFT architecture, scan insertion, ATPG pattern generation, and post-silicon support for AMD's Radeon processors.
Role type
Senior IC DFT Engineer (Scan Insertion | ATPG | MBIST)
Builds
Front-end design and integration for next-gen Radeon processors
Domain
Semiconductor / Hardware Design
Required skills
DFT architecture implementation, Scan insertion, ATPG pattern generation, Gate-level simulation, Test coverage analysis, Yield learning, IEEE1500, JTAG 1149.x, Memory BIST, Mentor testkompress, Synopsys Tetramax/DFTMAX, VCS simulation, Perl/Shell scripting, Verilog RTL design
Preferred skills
Senior silicon design collaboration, First-pass silicon success focus
Technologies
VCS, Perl, Shell, Verilog, IEEE1500, JTAG 1149.x, Mentor testkompress, Synopsys Tetramax/DFTMAX
Responsibilities
Implement and verify DFT architecture and features, Perform scan insertion and ATPG pattern generation, Verify ATPG patterns with gate-level simulation, Analyze test coverage and test cost reduction, Provide post-silicon support for bring-up and yield enhancement
Seniority
Senior, hands-on IC
