Formal Validation Engineer
Core
Develop comprehensive formal verification test plans, prove design properties, and find bugs for Apple Silicon's SOC and IP design blocks.
Role type
Senior IC formal validation engineer (hardware verification)
Builds
Formal verification test plans, optimized formal models, and verification code bases for CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory, Security, and Peripheral IPs.
Domain
Semiconductor hardware design and formal methods
Required skills
Digital hardware design principles, Model checking, Formal methods, Hardware description languages (Verilog, VHDL), Scripting (Python, Perl, TCL), Computer architecture analysis, SoC analysis
Preferred skills
N/A
Technologies
Verilog, VHDL, Python, Perl, TCL
Responsibilities
Develop comprehensive formal verification test plans, Prove properties of the design and find design bugs, Craft novel solutions for verifying complex design micro-architectures, Develop and implement re-usable and optimized formal models and verification code base, Architect correct-by-construction design methodologies, Work closely with design teams to improve micro-architecture
Seniority
Senior, hands-on IC
