Technical Lead – LINT, CDC & RDC Verification
Core
Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development; drive deployment and qualification of EDA solutions; debug complex structural verification issues.
Role type
Senior IC verification engineer (SoC/IP signoff)
Builds
Enterprise-wide signoff methodologies and verification infrastructure for complex SoC and IP programs
Domain
Semiconductor design verification (SoC/IP)
Required skills
SoC/IP design verification, Signoff methodology, EDA tool deployment, Siemens Questa CDC/RDC/Lint, Synopsys VC SpyGlass, Tcl/Python/Perl automation, CI/CD integration, Waiver management, Root-cause analysis
Preferred skills
Mentorship, Technical training, Stakeholder collaboration
Technologies
Questa Lint, VC SpyGlass, Questa CDC, VC SpyGlass CDC, Tcl, Python, Perl
Responsibilities
Define and maintain LINT, CDC, and RDC signoff methodologies; Execute CDC and RDC signoff and drive closure; Perform RTL quality checks and resolve violations; Develop custom rule sets and automation scripts; Lead technical reviews and provide guidance on structural verification issues; Mentor engineers and drive technical training programs
Seniority
Senior, hands-on IC
