Design Verification Engineer
Core
Create coverage-driven verification plans, test benches, and test infrastructure for High-Efficiency SOC Architecture and standard SOC peripherals.
Role type
Design Verification Engineer (SoC)
Builds
Portable test benches, sequences, and test infrastructure for System on Chip (SoC) designs
Domain
Semiconductor / SoC Design
Required skills
System Verilog, Verilog, VHDL, C/C++, UVM, Linux/Unix, Perl, Bash, Python, Cadence, Synopsys simulators
Preferred skills
N/A
Technologies
UVM, Cadence, Synopsys, System Verilog, Verilog, VHDL, C/C++, Perl, Bash, Python
Responsibilities
Create coverage driven verification plans from specifications; Create IP level module and sub-system verification plan, TB, portable test benches, sequences, and test infrastructure; Architect UVM-based highly reusable test benches integrating complex multi-instance VIPs, sub-system test benches, and test suites to SOC level; Collaborate closely with DV methodology architects to improve verification flow.
Seniority
Mid-Senior, hands-on IC
