Design for Test Engineer
Core
Verify advanced Design for Test (DFT) functions, including scan and core level testing, and conduct emulation and PAGATE level verification for hardware projects.
Role type
Senior IC verification engineer (DFT)
Builds
Verified hardware designs ready for silicon
Domain
Semiconductor hardware verification
Required skills
Scan chain verification, ATPG pattern generation, SystemVerilog, Verilog, waveform analysis (Verdi/DVE), bug triage, RTL code analysis, verification automation scripting (Perl/Python/Tcl), computer architecture knowledge
Preferred skills
N/A
Technologies
SystemVerilog, Verilog, Synopsys Verdi, JIRA/Radar, Perl, Python, Tcl
Responsibilities
Conduct scan dump verification on RTL level, perform emulation and PAGATE level verification, identify and remediate bugs by collaborating with designers, support teams with post-design verification issues, review design specifications against RTL code
Seniority
Senior, hands-on IC
