Senior Principal Engineer-DFT
Core
Architecting, leading, and implementing Design-for-Test (DFT) methodology for complex mixed-signal System-on-Chips (SoCs) across multiple generations, including architecture definition, IP-DFT, and post-silicon bringup.
Role type
Senior Principal DFT Lead (Mixed-Signal ASIC)
Builds
Next-generation Optical DSP ASICs for hyperscale data center, enterprise, and AI infrastructure markets.
Domain
Semiconductor / ASIC Design / Digital Circuit Design
Required skills
DFT architecture definition, Mixed-signal SoC design, SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug, Digital Circuit Design, Logic Design, Cadence/Mentor/Synopsys toolset (Genus, Modus, NCSim, DC, Tessent, Spyglass, Tmax), Python/Perl/Tcl/C-Shell scripting
Preferred skills
ASIC design experience, Advanced process node knowledge (TSMC)
Technologies
TSMC, Cadence, Mentor, Synopsys, Genus, Modus, NCSim, DC, Tessent, Spyglass, Tmax, Python, Perl, Tcl, C-Shell
Responsibilities
Define and enhance DFT methodologies and tools, mentor and guide a full team of DFT engineers, execute DFT/DFX features implementation, perform validation and post-silicon debug.
Seniority
Senior, hands-on IC technical leader
