Design Verification Engineer
Core
Verify mixed-signal IC designs (power management, LDOs, data converters, references, I/O, clock circuits) using analog circuits, Verilog-AMS, and Verilog RTL simulations to ensure high-quality silicon for IC chips and IPs.
Role type
Design Verification Engineer (Mixed-Signal IC)
Builds
Mixed-signal IC designs and verification environments for Apple silicon
Domain
Semiconductor / Mixed-Signal Analog & Digital IC Design
Required skills
Verilog-AMS, Verilog RTL, analog circuit design, mixed-signal simulation, EDA tools (Cadence, Synopsys), verification planning, test pattern development, failure debugging, coverage analysis
Preferred skills
N/A
Technologies
Cadence, Synopsys, Verilog-AMS, Verilog RTL
Responsibilities
Review specifications and craft verification plans; execute verification plans from beginning to end including testing bench bring-up and regressions; develop verification environments including stimuli, checkers, assertions, and trackers; debug mixed-signal IC designs and simulator issues; evaluate and benchmark simulator performance; reproduce and triage issues reported by tool users
Seniority
Mid-level, hands-on IC
