Design Verification
Core
Verify Mixed Signal blocks (Analog-Digital Convertors, Phase-locked Loops) by developing testbenches, checkers, and behavioral models to ensure circuit correctness and robustness.
Role type
Senior IC design verification engineer (mixed-signal)
Builds
Verified Mixed Signal and Digital testbenches, checkers, and behavioral models for SOC architectures
Domain
Semiconductor / Mixed-Signal IC Design
Required skills
System Verilog, UVM, Python, Cadence Virtuoso, Xcelium, SPECTRE, I2C, SPI, AHB, Unix/Linux shell scripting
Preferred skills
N/A
Technologies
UVM, System Verilog, Python, Cadence Virtuoso, Xcelium, SPECTRE, vManager
Responsibilities
Develop top/block level Mixed Signal and Digital testbench and generating directed/constrained-random tests; Develop checkers/assertions in System Verilog to capture incorrect signal behaviors; Validate correctness of models by analyzing waveforms in Xcelium and comparing SPECTRE/System Verilog results; Debug failures of circuit simulation tests and fix testbench/model/checker issues; Track and analyze functional coverages of all signals with vManager; Write automation scripts in Python for flow; Extract information from design documents to develop digital mixed-signal behavioral models; Maintain Virtuoso Hierarchy Editor config to generate netlists; Coordinate with designers to sign-off simulation results.
Seniority
Mid-level, hands-on IC
