VLSI CAD Engineer
Core
Execute RTL regression tests, analyze coverage data, and build ML models to predict test failures and optimize verification resource allocation.
Role type
VLSI CAD Engineer (Verification)
Builds
RTL regression systems and ML-based verification optimization tools
Domain
Semiconductor / VLSI Design / Machine Learning
Deliverable
production ML models
Required skills
RTL regression testing, Verilog/SystemVerilog, UVM, HDL simulation, coverage analysis, RTL debugging, automation scripting, machine learning model development, performance optimization, cloud-based verification platforms
Preferred skills
N/A
Technologies
Verilog, SystemVerilog, UVM, HDL simulators, debuggers, task parallelism libraries, cloud verification platforms
Responsibilities
Execute RTL regression tests using industry-standard verification tools; Monitor regression results and analyze coverage data; Utilize debuggers to step through RTL code and identify issues; Develop and implement new solutions to address regression issues; Build ML models that predict test failures or optimize resource allocation; Implement performance optimizations in regression runs; Maintain and enhance the existing RTL regression system; Implement automation scripts to streamline regression setup, execution, and result analysis
Seniority
Mid-level, hands-on IC
