Hardware Engineer
Core
Design, implement, and debug memory SoftModels for simulation, emulation, and prototyping environments; debug verification flows and benchmark test results.
Role type
hardware verification engineer (memory protocols)
Builds
memory SoftModels and verification flows for simulation and emulation
Domain
Electronic Design Automation (EDA) / Semiconductor design
Required skills
Verilog, SystemVerilog, digital hardware design, FPGA design flows, memory protocol standards (JEDEC), scripting (Shell, Perl, Python, Tcl/Tk)
Preferred skills
Siemens DISW tools, prototyping or emulation experience
Technologies
Verilog, SystemVerilog, JEDEC, VirtuaLAB, DISW, Python, Tcl/Tk, Shell, Perl
Responsibilities
Design and debug memory SoftModels for simulation and emulation; debug simulation- and emulation-based verification flows; test VirtuaLAB solution portfolio; monitor and analyze test results and perform benchmarking
Seniority
Mid-level, hands-on IC
