Design Verification Engineer
Core
Pre-silicon verification and post-silicon validation of custom silicon components using constrained random stimulus, scoreboards, checkers, and assertions.
Role type
Design Verification Engineer
Builds
Custom silicon components and verification IP (VIP)
Domain
Semiconductor / Hardware Design
Required skills
System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification, C/C++, Python scripting, functional coverage closure, test plan development, debugging failures
Preferred skills
Experience with full product cycle from definition to silicon, IP/block or subsystem level test plans, integrating test benches and checkers
Technologies
System Verilog, UVM, Python, C/C++
