Senior Principal Design Verification Engineer
Core
Lead verification of complex SoC, IP, and modem subsystem designs, influencing architecture and methodology across global engineering organizations.
Role type
Senior Principal Design Verification Engineer
Builds
Scalable and reusable SystemVerilog/UVM verification environments for semiconductor products
Domain
Semiconductor / SoC Design Verification
Required skills
SystemVerilog, UVM, SVA, constrained-random verification, coverage-driven methodologies, Python, Perl, Tcl, Shell, debugging, root-cause analysis, leadership
Preferred skills
USB, DisplayPort, USB Type-C, USB-PD, I2C, SPMI, SPI protocols, modem verification, formal verification, assertion-based verification, low-power verification (UPF/CPF)
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, Shell
Responsibilities
Own verification strategy, planning, execution, and signoff; Architect scalable verification environments; Develop verification plans, coverage models, and assertions; Drive coverage closure; Debug complex design issues; Mentor verification engineers; Coordinate across global sites
Seniority
Principal, hands-on IC with leadership
