Senior Design Verification Engineer
Core
Develop robust, scalable verification environments for highly complex ASIC/SoC designs to ensure they work exactly as intended.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Next-generation memory and storage ASICs (DRAM/NAND/SSD)
Domain
Semiconductor / Memory and Storage
Required skills
UVM, SystemVerilog, constrained-random verification, functional debugging, coverage closure, analytical skills
Preferred skills
mixed-signal modeling, DRAM/NAND/SSD protocols, AI-assisted verification tools, automation
Technologies
UVM, SystemVerilog, AI-assisted workflows
Responsibilities
Develop and maintain UVM-based SystemVerilog verification environments; Define and execute block and system-level verification plans; Debug complex functional and integration issues; Drive coverage closure and improve verification quality metrics; Explore and adopt AI-assisted techniques to improve productivity.
Seniority
Senior, hands-on IC
