Design for Test Engineer
Core
Develop DFT verification plans, implement test benches and assertions, debug RTL/gate-level simulations, and generate ATE patterns for ASIC designs.
Role type
Design for Test (DFT) Engineer
Builds
Verification plans, test benches, assertions, ATE patterns, and simulation reports for ASICs
Domain
Semiconductor / VLSI Design
Required skills
VLSI Design, Verilog, Perl/Python/Tcl scripting, CMOS circuits, Digital Logic Gate Analysis, Test Automation, Timing Analysis, Synthesis, Simulation, DFT knowledge, Memory Circuit verification
Responsibilities
Review architecture and design specifications, extract design features, develop attributes and verification plans, work with designers to verify DFT implementation, implement test benches and assertions, debug failures and run RTL/gate-level simulations, generate Collaterals and reports, handle schedules and support multi-functional engineering effort, assist in verification flows and automation scripts, work with test engineers to bring up functional and structural patterns for Analog IPs and DFT features on Silicon
Seniority
Mid-level, hands-on IC
