Senior Lead Engineer - Design Verification
Core
Senior verification leader defining architecture and methodology for next-generation FPGA, programmable SoC, and platform solutions.
Role type
Senior Lead Engineer - Design Verification
Builds
Scalable verification environments, verification IP, and coverage-driven closure for complex digital subsystems and full-chip integrations.
Domain
Semiconductor / FPGA / SoC / Digital Design
Required skills
SystemVerilog, UVM, constrained-random verification, assertions, coverage-driven closure, verification architecture, RTL design, simulation, debug, regression management, hardware development flows
Preferred skills
C/C++, SystemC, Python, Tcl, Perl, shell scripting, formal verification, low-power verification, CDC/RDC analysis, performance verification, full-chip verification, firmware/software co-verification, post-silicon debug
Technologies
SystemVerilog, UVM, C, C++, SystemC, Python, Tcl, Perl
Responsibilities
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems; Define comprehensive verification plans translating architectural intent into measurable objectives; Architect and develop scalable, reusable verification environments and VIs; Establish and advance verification methodology, coding standards, and automation; Drive verification closure using functional, code, assertion, and cross coverage; Partner with architecture and RTL design teams to clarify specifications and resolve issues; Lead debug of simulation, integration, and system-level failures; Develop and maintain scalable simulation, regression, build, and reporting infrastructure; Provide technical mentorship and verification leadership.
Seniority
Senior, hands-on IC
