Sr DFT Engineer
Core
Design, implement, and verify DFT architectures for complex SoCs to ensure robust testability and high-quality silicon.
Role type
Senior IC DFT Engineer
Builds
Testable SoC silicon with integrated scan, MBIST, LBIST, and boundary scan
Domain
Semiconductor / Digital SoC Design
Required skills
DFT methodologies (Scan, MBIST, LBIST, JTAG), ATPG tools, UPF/CPF low-power DFT, fault models, physical design constraints, silicon debug, ATE bring-up
Preferred skills
SoC-level DFT experience, high-speed interfaces, mixed-signal DFT
Technologies
ATPG tools, UPF, CPF, JTAG
Responsibilities
Define and implement DFT architecture for SoCs, Develop and integrate scan insertion and test compression, Implement memory BIST and logic BIST strategies, Collaborate with RTL and physical design teams for DFT insertion, Perform DFT verification at RTL and gate-level, Work with ATE teams for test program development, Optimize test coverage and test time
