CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)
Core
Design and verification of advanced RISC-V processor IP, focusing on microarchitecture, RTL implementation, and functional verification.
Role type
Intern, CPU IP Design & Verification Engineer
Builds
RISC-V CPU cores for semiconductor manufacturing
Domain
Semiconductor / CPU Design
Required skills
SystemVerilog, Python, C/C++, digital logic design, computer architecture, CPU fundamentals (pipelines, caches, memory hierarchy), scripting for automation
Preferred skills
RISC-V ISA knowledge, UVM, constrained-random verification, FPGA/ASIC project experience, Linux, Git, assembly programming
Technologies
SystemVerilog, Python, C/C++, UVM, Linux, Git
Responsibilities
Support RISC-V CPU microarchitecture and RTL design; Develop verification tests, assertions, and functional coverage; Run simulations and debug failures; Support power, performance, and area analysis; Develop automation scripts; Document technical results
Seniority
Intern
